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PCB/HDL Mentor Graphics Tech Day

PCB/HDL Mentor Graphics Tech Day

Warszawa, 12 września 2018r.

Gamma jako autoryzowany dystrybutor oprogramowania
firmy Mentor Graphics w Polsce

ma przyjemność zaprosić Państwa na spotkanie PCB/HDL Mentor Graphics Tech Day

Wymagania wobec nowoczesnych urządzeń elektronicznych powodują, że coraz większe wymagania dotyczą także stosowanego oprogramowania ECAD. Doskonale widać to w przypadku oprogramowania do PCB oraz FPGA. Dla oprogramowania PCB nie wystarczają już doskonałe metody edycji połączeń, ale również zdolność do rozwiązywania problemów z zakresu Signal Integrity, Power Integrity, emisji elektromagnetycznej czy zagadnień termicznych oraz chłodzenia. Narzędzia do FPGA/ASIC poza tworzeniem i symulacją kodu RTL umożliwiają dzisiaj implementację coraz bardziej zaawansowanych metod automatycznej weryfikacji funkcjonalnej czy formalnej.

Niezbędne staje się też posługiwanie odpowiednimi narzędziami pozwalającymi na definiowanie i śledzenie wymagań stawianym urządzeniu na różnych etapach projektowania oraz weryfikacji założeń realizowanych często przez różne zespoły.

Stosowanie nowoczesnego oprogramowania daje wymierne korzyści miedzy innymi dramatycznie skracając czas testowania kolejnych prototypów oraz zmniejszając ich liczbę. Te i inne zagadnienia postaramy się przybliżyć Państwu na przykładzie oferowanego oprogramowania firmy Mentor Graphics.

Zajęcia poprowadzą w języku angielskim Inżynierowie z firm
Mentor oraz Gamma.

Warszawa, 12 września 2018r.

Agenda spotkania PCB/HDL Mentor Graphics Tech Day

Planowany czas


8:30 - 9:00


9:00 - 9:15


9:15 - 10:15

From the product specification to the final product - presenter Stefan Bauer

  • IBM DOORS is nearly universally used not only by the Mil-Aero industry to capture and manage system level requirements. On the other hand, at the detail design stage DOORS is considered by most engineering teams to be not agile enough and is seldom used by the CCA board, software, FPGA/ASIC design and verification teams. The most popular detail design stage’s requirement capture tool is Microsoft Office.  Thus, too often there can exist a requirement tracing gap at the boundary between the system engineering and the PCB, SW, digital electronics design teams.  Mentor Graphics’ ReqTracer solves this problem with an automated solution for tracing requirements out of DOORS into MS Office documents, spreadsheets, DxD schematic capture, source code targeting software and hardware.  When the verification team tag their test bench code and test result messages or assertions, then ReqTracer can be used to automatically show system level requirements traceability continuously from DOORS down through multiple levels of elaborated requirements captured outside of DOORS ending with the test result logs.

10:15 - 10:30

Coffee Break

10:30 - 12:00

  • PCB Track - presenter Olivier Arnaud: No compromise to limit your ability and creativity with PADS® Professional.

    • Until now, your choice of PCB design tools has been a frustrating compromise. High-end enterprise solutions that handle design complexity come with too much unnecessary overhead and the associated challenges of usability and cost of ownership. Desktop solutions are easier to use and have lower cost, but productivity bogs down as design complexity increases.
    • PADS Professional provides the tools you need for the problems you have to solve:
      • Having trouble achieving aggressive PCB design schedule?
      • Current tools running out of steam on complex designs?
      • Tools keeping up with the newest PCB technology?
      • Competitors beating you to market?
      • Spending too much time cleaning up your layout before release?
    • The solution is PADS Professional. It brings you the best of both worlds — based on powerful Mentor Xpedition technology in combination with a focus on ease of adoption, ease of learning, ease of use, and affordability. PADS Professional directly addresses your challenges and provides the tools and horsepower to solve them.
  • FPGA Track - presenter Stefan Bauer: Staying competitive with modern FPGA verification methodologies.

    • FPGA vendors continue to push the boundaries creating innovative new ways for users to efficiently design into today's increasingly complex FPGAs. Recent industry surveys show a direct correlation between a designs complexity and a program’s inability to deliver a working FPGA on schedule. Additionally, time spent in verification is trending upwards while simultaneously, an increasing number of costly bugs are not being found until before going to production. This presentation arms engineers with the advanced verification methodology they need to deliver working designs within a predictable schedule in today’s quickly evolving FPGA market.
    • Advanced verification is a broad topic with many diverse areas. This presentation focuses on three main areas:
      • Automation enables engineers to focus on the important, and honestly more fun, tasks while leaving the boring repetitive tasks like test bench creation and parsing through test results to a computer.
      • Verification IP lets engineers avoid sinking valuable time writing and debugging models or BFMs for industry standard interfaces and become immediately productive exercising the custom logic that needs it.
      • Coverage helps engineers and managers create a plan for verification which will ensure high quality and predictable schedules.
    • After attending this presentation you will walk away with an understanding of how and why traditional verification approaches are leaving engineers to toiling in the lab and making excuses to customers. Join Stefan Bauer, one of Mentor’s verification experts, on this exciting journey to streamline your FPGA verification approaches!

12:00 - 13:15


13:15 - 14:45

  • PCB Track - presenter Olivier Arnaud: Extend PADS® Professional capabilities to meet your needs.

    • PADS Professional can grow as the needs of your designs grow. As technology requirements and design complexities continue to expand, additional capabilities and functions can be added to the entire flow that ensure you are able to keep pace with the latest devices, as well as higher speed and advances in technology.
    • Benefiting from Mentor the best in class HyperLynx and FloTHERM-XT technologies, advanced analysis capabilities in various domains such as Signal Integrity, Power Integrity and Electronics cooling can be added to extend the PADS Professional core functionality and bring you even more competitive advantages to be succesful.
    • Discover some of the possible extensions listed below:
      • DDR Analysis
      • DRC analysis for EMI & electrical checks
      • DC Drop
      • Electronics cooling
  • FPGA Track - presenter Stefan Bauer: Exhaustive automated formal solutions for FPGA verification challenges.

    • Wouldn’t it be great if you could begin serious verification before a testbench was available? Even better, what if your verification process gave you exhaustive results? Formal verification delivers on both counts, and today formal apps enable regular engineers to make use of classical formal techniques to explore their design’s behavior in an intuitive, interactive manner. Applying formal early shortens the overall verification cycle by finding and fixing most bugs during development instead of late in the verification game. Furthermore formal techniques easily find bugs that are often never found in functional simulation.
    • Some examples of its application include: identifying unreachable code, identifying errors that have to do with clock domain crossings, creating ""witness waveforms"" that show how to exercise hard to reach code, ensuring your design is secure, and proving error correction logic is correct.

14:45 - 15:00

Coffee Break

15:00 - 16:00

IO Optimizer - presenter Olivier Arnaud: Bridging the domains of FPGA design and PCB design.

  • IO Optimizer integrates the different worlds of FPGA and PCB design processes into a single system-design process that helps customers maintain their competitive edge and assure their continuing success. Improve communication & design synchronization across the design team and optimize multiple FPGA’s IO in relation to the PCB design while adhering to the FPGA vendor’s device rules.

    Enable frequent I/O pin swaps by generating & maintaining PCB schematics and symbols for the FPGA devices automatically. Automatically optimize busses on the PCB trace layout to minimize trace length and cross-overs resulting in reduced via count, potential reduction of PCB signal layer count and overall improved signal timing margins and signal quality.

    Also part of IO Optimizer, FPGA part wizard add-on brings the possibility to accurately and efficiently create your high pin count FPGA device parts in minutes.

    IO Optimizer benefits reduce design cycle-time enormously while improving the maximum operating frequencies of the bus traces. As a result, manufacturing costs go down and product reliability goes up.

16:00 - 16:15

Final Remarks, Q&A and prize drawing

Miejsce spotkania

Warsaw Trade Tower

ul. Chłodna 51, 00-867 Warszawa
Jak dojechać?

Godziny spotkania: 9:00-16:15 (dwie przerwy kawowe + lunch)

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